LP_CMP_ISRC_SEL=sel0, REG_FBK_SEL=reg_fbk_sel0, LOOPCTRL_HST_THRESH=low_hyst_thresh, REG_RLOAD_SW=loadR_disconnect, LOOPCTRL_EN_HYST=disable
DCDC Register 1
| REG_FBK_SEL | Select the feedback point of the internal regulator 0 (reg_fbk_sel0): The regulator outputs 1.0V with 1.2V reference voltage 1 (reg_fbk_sel1): The regulator outputs 1.1V with 1.2V reference voltage 2 (reg_fbk_sel2): The regulator outputs 1.0V with 1.3V reference voltage 3 (reg_fbk_sel3): The regulator outputs 1.1V with 1.3V reference voltage |
| REG_RLOAD_SW | This controls the load resistor of the internal regulator of DCDC 0 (loadR_disconnect): Load resistor disconnected 1 (loadR_connect): Load resistor connected |
| LP_CMP_ISRC_SEL | Low Power Comparator Current Bias 0 (sel0): 50 nA 1 (sel1): 100 nA 2 (sel2): 200 nA 3 (sel3): 400 nA |
| LOOPCTRL_HST_THRESH | Increase Threshold Detection 0 (low_hyst_thresh): Lower hysteresis threshold (about 2.5mV in typical, but this value can vary with PVT corners 1 (high_hyst_thresh): Higher hysteresis threshold (about 5mV in typical) |
| LOOPCTRL_EN_HYST | Enable Hysteresis 0 (disable): Disable hysteresis in switching converter common mode analog comparators 1 (enable): Enable hysteresis in switching converter common mode analog comparators |
| VBG_TRIM | Trim Bandgap Voltage |